/*
* $Id$
*/
#ifndef _PCI_PIO_H_
#define _PCI_PIO_H_
#define PCI_TYPE_1 1
#define PCI_TYPE_2 2
#define PCI_BUSSES 16
#define PCI_BASE 0xcf8
#define PCI_INDEX_REG 0xcfa
#define PCI_T1_INDEX_REG 0xcfc
#define BUS_ADDRESS 0x80000000
#define V_BUS_ADDRESS 0xc000
int pci_get_type(void);
int pci_init(void);
int pci_find_devices(struct pci_conf_t *pci_conf[]);
int pci_t1_read_config(struct pci_conf_t *pci_conf, unsigned int dev);
int pci_t1_write_config(struct pci_conf_t *pci_conf, unsigned int dev);
int pci_t2_read_config(struct pci_conf_t *pci_conf, unsigned int dev);
int pci_t2_write_config(struct pci_conf_t *pci_conf, unsigned int dev);
struct pci_device_id_t {
u16 vendor_id;
u16 device_id;
const u8 *name;
};
struct pci_conf_t {
u16 vendor_id;
u16 device_id;
struct command {
u16 response_io : 1,
response_memory : 1,
bus_master : 1,
special_cycles : 1,
invalidate : 1,
vga_pal_snoop : 1,
parity : 1,
wait_cc : 1,
system_error : 1,
back2back_c : 1,
fast_back_c : 1,
res : 6;
};
struct status {
u16 res_low : 4,
capability_list : 1,
fast_bus : 1, /* 66MHz PCI bus */
user_def_features : 1,
fast_back_c : 1,
parity : 1,
devsel_timing : 2, /* 0=fast, 1=medium, 2=slow */
device_target_abort : 1,
recv_target_abort : 1,
master_abort_stat : 1,
signal_sys_err : 1,
detected_parity : 1;
};
u8 revision_code,
programming_interface;
u16 class;
u8 cache_line_size,
latency_timer, /* bit 0-2 res */
header_type,
bist; /* ??? */
u32 addr[2];
u8 header;
};
struct pci_dev_conf_t{
u32 addr[4],
cardbus_cis;
u16 subsystem_vendor_id,
subsystem_id;
u32 rom_address_enable : 1,
reserved : 10,
rom_address : 21;
u8 capability_list,
reserved2 : 6,
interrupt_line,
interrupt_pin,
minimum_granularity,
max_latency;
};
#define PCI_CAPABILITY_LIST_ID 0
/* Power Management. */
#define PCI_CAPABILITY_ID_PM 0x01
/* Accelerated Graphics Port. */
#define PCI_CAPABILITY_ID_AGP 0x02
/* Next capability in the list. */
#define PCI_CAP_LIST_NEXT 1
/* Device classes and subclasses. */
#define PCI_CLASS_NOT_DEFINED 0x0000
#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
#define PCI_BASE_CLASS_STORAGE 0x01
#define PCI_CLASS_STORAGE_SCSI 0x0100
#define PCI_CLASS_STORAGE_IDE 0x0101
#define PCI_CLASS_STORAGE_FLOPPY 0x0102
#define PCI_CLASS_STORAGE_IPI 0x0103
#define PCI_CLASS_STORAGE_RAID 0x0104
#define PCI_CLASS_STORAGE_OTHER 0x0180
#define PCI_BASE_CLASS_NETWORK 0x02
#define PCI_CLASS_NETWORK_ETHERNET 0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
#define PCI_CLASS_NETWORK_FDDI 0x0202
#define PCI_CLASS_NETWORK_ATM 0x0203
#define PCI_CLASS_NETWORK_OTHER 0x0280
#define PCI_BASE_CLASS_DISPLAY 0x03
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_CLASS_DISPLAY_XGA 0x0301
#define PCI_CLASS_DISPLAY_OTHER 0x0380
#define PCI_BASE_CLASS_MULTIMEDIA 0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
#define PCI_BASE_CLASS_MEMORY 0x05
#define PCI_CLASS_MEMORY_RAM 0x0500
#define PCI_CLASS_MEMORY_FLASH 0x0501
#define PCI_CLASS_MEMORY_OTHER 0x0580
#define PCI_BASE_CLASS_BRIDGE 0x06
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
#define PCI_CLASS_BRIDGE_EISA 0x0602
#define PCI_CLASS_BRIDGE_MC 0x0603
#define PCI_CLASS_BRIDGE_PCI 0x0604
#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
#define PCI_CLASS_BRIDGE_NUBUS 0x0606
#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
#define PCI_CLASS_BRIDGE_OTHER 0x0680
#define PCI_BASE_CLASS_COMMUNICATION 0x07
#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
#define PCI_BASE_CLASS_SYSTEM 0x08
#define PCI_CLASS_SYSTEM_PIC 0x0800
#define PCI_CLASS_SYSTEM_DMA 0x0801
#define PCI_CLASS_SYSTEM_TIMER 0x0802
#define PCI_CLASS_SYSTEM_RTC 0x0803
#define PCI_CLASS_SYSTEM_OTHER 0x0880
#define PCI_BASE_CLASS_INPUT 0x09
#define PCI_CLASS_INPUT_KEYBOARD 0x0900
#define PCI_CLASS_INPUT_PEN 0x0901
#define PCI_CLASS_INPUT_MOUSE 0x0902
#define PCI_CLASS_INPUT_OTHER 0x0980
#define PCI_BASE_CLASS_DOCKING 0x0A
#define PCI_CLASS_DOCKING_GENERIC 0x0A00
#define PCI_CLASS_DOCKING_OTHER 0x0A01
#define PCI_BASE_CLASS_PROCESSOR 0x0B
#define PCI_CLASS_PROCESSOR_386 0x0B00
#define PCI_CLASS_PROCESSOR_486 0x0B01
#define PCI_CLASS_PROCESSOR_PENTIUM 0x0B02
#define PCI_CLASS_PROCESSOR_ALPHA 0x0B10
#define PCI_CLASS_PROCESSOR_POWERPC 0x0B20
#define PCI_CLASS_PROCESSOR_CO 0x0B40
#define PCI_BASE_CLASS_SERIAL 0x0C
#define PCI_CLASS_SERIAL_FIREWIRE 0x0C00
#define PCI_CLASS_SERIAL_ACCESS 0x0C01
#define PCI_CLASS_SERIAL_SSA 0x0C02
#define PCI_CLASS_SERIAL_USB 0x0C03
#define PCI_CLASS_SERIAL_FIBER 0x0C04
#define PCI_CLASS_HOT_SWAP_CONTROLLER 0xFF00
#define PCI_CLASS_OTHERS 0xFF
#endif /* _PCI_PIO_H_ */
