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<definition>uInt32 pciConfig::base[6]</definition>
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<definition>uInt8 pciConfig::baseClass</definition>
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<definition>uInt8 pciConfig::bus</definition>
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<name>bus</name>
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<definition>uInt8 pciConfig::cacheLineSize</definition>
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<name>cacheLineSize</name>
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<detaileddescription>
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<definition>uInt16 pciConfig::command</definition>
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<name>command</name>
<briefdescription>
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<definition>uInt8 pciConfig::dev</definition>
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<briefdescription>
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<definition>uInt16 pciConfig::deviceId</definition>
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<name>deviceId</name>
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<definition>uInt8 pciConfig::func</definition>
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<name>func</name>
<briefdescription>
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<detaileddescription>
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<inbodydescription>
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<definition>uInt8 pciConfig::headerType</definition>
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<name>headerType</name>
<briefdescription>
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<detaileddescription>
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<inbodydescription>
</inbodydescription>
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<definition>uInt8 pciConfig::interface</definition>
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<name>interface</name>
<briefdescription>
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<detaileddescription>
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<definition>uInt8 pciConfig::irq</definition>
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<name>irq</name>
<briefdescription>
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<detaileddescription>
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<inbodydescription>
</inbodydescription>
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<definition>uInt8 pciConfig::latencyTimer</definition>
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<briefdescription>
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<detaileddescription>
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<inbodydescription>
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<definition>uInt8 pciConfig::revisionId</definition>
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<name>revisionId</name>
<briefdescription>
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<inbodydescription>
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<definition>uInt32 pciConfig::size[6]</definition>
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<name>size</name>
<briefdescription>
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<definition>uInt16 pciConfig::status</definition>
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<definition>uInt8 pciConfig::subClass</definition>
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<definition>uInt16 pciConfig::subsys</definition>
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<definition>uInt16 pciConfig::subsysVendor</definition>
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