#define ATA_REG_CNT (2) #define ATA_REG_SECT (3) #define ATA_REG_STAT (7) #define ATA_REG_SLCT (0x206) #define ATA_REG_DRVHD (6) #define WAIT_READY (30) #define ATA_REG_LOCYL (4) #define ATA_REG_HICYL (5) #define ATA_FLG_ATAPI (0x0001) #define ATA_FLG_LBA (0x0002) #define ATA_FLG_DMA (0x0004) #define ATA_CMD_PID (0xA1) #define ATA_REG_CMD (7) #define WAIT_PID (3) #define ATA_CMD_ID (0xEC) #define WAIT_ID (30000) #define ATA_REG_DATA (0) #define ATA_CAP_LBA (0x0001) typedef unsigned char __u8; typedef unsigned short __u16; typedef unsigned long __u32; typedef struct { __u16 vendor_id,device_id,command,status; __u8 revision_id,interface,sub_class,base_class,cache_line_size; __u8 latency_timer,header_type,bist; __u8 bus,dev,func,irq; __u32 base[6]; __u32 size[6]; int is_bridge; } pci_cfg_t; typedef struct { __u16 Config,PhysCyls,Res2,PhysHeads,UnfBytesPerTrack; __u16 UnfBytesPerSect,PhysSects,Vendor0,Vendor1,Vendor2; __u8 SerialNum[20]; __u16 BufType,BufSize,ECCBytes; __u8 FirmwareRev[8],Model[40],MaxMult,Vendor3; __u32 DwordIO; __u8 Vendor4,Capability; __u16 Res50; __u8 Vendor5,PIOMode,Vendor6,DMAMode; __u16 LogValid,LogCyls,LogHeads,LogSects; __u32 TotalSects; __u8 MultSect,MultSectValid; __u32 LBASects; __u16 DMAInfoSingle,DMAInfoMult,EIDEPIOModes,EIDEDMAMin; __u16 EIDEDmaTime,EIDEPIO,EIDEPIOIORdy,Res[187]; } ide_hwif_t; typedef struct { ide_hwif_t hwif; __u16 flags; __u8 sel; __u16 ioadr; __u8 multsect; __u16 sects,heads,cyls; __u32 lba_blocks; __u16 capabilities; __u16 status; __u16 irq; __u32 full_power_mode_enter_time; __u32 errors; __u16 mult_count; __u16 bytes_per_block; pci_cfg_t * pci_config; } ide_dev_t; void ideProbe(void); void irq14(); void irq15(); int ide_select(ide_dev_t * dev); void ide_probe_dev(ide_dev_t * dev); void ide_insw(__u16 Adr,__u16 * Data,__u16 Count); int ide_await_interrupt(__u32 mask,__u32 timeout); void ide_insw(__u16 Adr,__u16 * Data,__u16 Count); void set_irq_occured(__u32 m); void clear_irq_occured(void); int ide_check_lba_geometry(ide_dev_t * dev);